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Data Sheet
Table 26. ACCMODE Register (Address 0xE701)
Default
ADE7816
Bits
7
Bit Name
REVRPSEL
Value
0x0
Description
0: the sign of the reactive power is monitored on the A, B, and C channels.
1: the sign of the reactive power is monitored on the D, E, and F channels.
Bit 14 (CHANNEL_SEL) of COMPMODE must be set to the same current channels.
6
REVAPSEL
0x0
0: the sign of the active power is monitored on the A, B, and C channels.
1: the sign of the active power is monitored on the D, E, and F channels.
Bit 14 (CHANNEL_SEL) of COMPMODE must be set to the same current channels.
[5:4]
[3:2]
Reserved
VARACC[1:0]
0x00
0x00
These bits should be ignored and not modified.
00: signed accumulation for all reactive power measurements.
01: reserved.
10: reserved.
11: reserved.
[1:0]
WATTACC[1:0]
0x00
00: signed accumulation for all active power measurements.
01: reserved.
10: reserved.
11: reserved.
Table 27. LCYCMODE Register (Address 0xE702)
Default
Bits
7
6
Bit Name
Reserved
RSTREAD
Value
0x0
0x1
Description
Reserved. This bit does not control any functionality.
Enables read-with-reset for all energy registers. Note that this bit has no function in line cycle
accumulation mode and should be set to 0 when this mode is in use.
[5:4]
3
2
1
0
Reserved
ZX_SEL
Reserved
LVAR
LWATT
0x0
0x0
0x0
0x0
0x0
These bits should be ignored.
Enables the voltage channel zero-crossing counter for line cycle accumulation mode.
These bits should be ignored.
Enables the reactive energy line cycle accumulation mode.
Enables the active energy line cycle accumulation mode.
Table 28. HSDC_CFG Register (Address 0xE706)
Default
Bits
[7:6]
5
Bit Name
Reserved
HSAPOL
Value
0x00
0x0
Description
These bits should be ignored.
0: SS/HSA output pin is active low (default).
1: SS/HSA output pin is active high.
[4:3]
HXFER[1:0]
0x00
00 = reserved.
01 = HSDC transmits current and voltage waveform data.
10 = reserved.
11 = reserved.
2
HGAP
0x0
0: no gap is introduced between packages (default).
1: a gap of seven HCLK cycles is introduced between packages.
1
HSIZE
0x0
0: HSDC transmits the 32-bit registers in 32-bit packages, most significant bit first (default).
1: HSDC transmits the 32-bit registers in 8-bit packages, most significant bit first.
0
HCLK
0x0
0: HSCLK = 8 MHz (default).
1: HSCLK = 4 MHz.
Table 29. CONFIG2 Register (Address 0xEC01)
Default
Bits
[7:2]
1
0
Bit Name
Reserved
I2C_LOCK
EXTREFEN
Value
0x0
0x0
0x0
Description
These bits should be ignored.
Serial port lock.
Set to 1 to use with an external reference.
Rev. A| Page 43 of 48
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